With the rapid growth of wireless and portable consumer electronic devices, there have been increasing demands for new technological advancements with more functions in battery-operated systems. This phenomenon has resulted in increasing design and verification challenges for low-power (low electric power consumption) applications.
The challenges include minimizing leakage power dissipation, designing efficient packaging and cooling systems for high-power integrated circuits, and verifying functionalities of low-power or no power situations early in the circuit design process. Such power management issues become even more critical in view of the continuous shrinking of device (transistor) dimensions with the next generation of semiconductor processing technology. Addressing such power management issues is critical in the integrated circuit design process for portable consumer electronic devices.
Existing power optimization and implementation techniques are typically applied at the physical implementation phase of the I.C. design process. Certain power management techniques can only be implemented at the physical level after circuit synthesis. These power management design techniques may significantly change the design intent, yet none of the intended behavior can now be captured in the RTL (Register Transfer Language) version of the design. This deficiency creates a gap in the RTL to Graphic Data System II (GDSII) implementation and verification flow where the original RTL can no longer be relied upon as a correct representation of the design, and thus cannot be used to verify the final netlist implementation containing power management implementations.
Therefore, there is a need for incorporating power information of the circuit to address the deficiencies of the existing design methodologies in the design process and especially as applicable to circuit testing. Specifically, there is a need for incorporating power information in the design process and applying the power information to the entire design flow of verification, validation, synthesis, test, physical synthesis, routing, analysis and signoff tool. In particular, there is a need to ensure that other portions of the integrated circuit are functional when one or more power domains are powered down, e.g. in an RTL design environment.
In more detail, in the state of the art integrated circuits typically have one or more designated test modes for manufacturing testing. This manufacturing testing typically is done at the wafer stage when the integrated circuits are still each a die in a full silicon wafer. Of course the tests can be applied after the wafer has been diced and even after the individual die have been packaged in integrated circuits. However it is typically performed early. This particular type of manufacturing testing is normally directed towards finding faulty circuit elements such as opens, shorts, or faulty transistors, but is not so limited.
In the actual circuit testing there are important power considerations for ICs which are intended to operate at low power such as in battery operated or other applications wherever power consumption is an issue. The common power format (CPF) further referred to below is a software design tool being introduced in the electronic design field for design and simulation of such low power circuits. Not only during operation but also during testing, power consumption is an issue for several reasons. First, the test equipment (ATE, automatic test equipment) normally used in the industry can only handle limited amounts of power being sourced or sunk from a particular wafer or a die. Hence the typical prior art approach in the test mode of having the integrated circuit or die fully powered up for testing is not practical. Further there is the issue of power droop, which is current-resistance drop at high applied power, which also interferes with testing. This testing typically involves what is called in the field ATPG or automatic pattern test generation, for applying test signals (vectors) to the device under test.